 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PD-94590 IP1201 Dual Output Full Function 2 Phase Synchronous Buck Power Block Features * * * * * * * * * * * * * * * 3.14V to 5.5V input voltage 0.8V to 3.3V output voltage 2 Phase Synchronous Buck Power Block 180 out of phase operation Single or Dual output capability Dual 15A maximum load capability Single 2 phase 30A maximum load capability 200-400kHz per channel nominal switching frequency Over Current Hiccup or Over Current Latch External Synchronization capability Overvoltage protection Independent soft start per output Over Temperature protection Internal features minimize layout sensitivity * Very small outline 15.5mm x 9.25mm x 2.6mm Integrated Power Semiconductors, PWM Control & Passives IP1201 Power Block Description The IP1201 is a fully optimized solution for medium current synchronous buck applications requiring up to 15A or 30A. The IP1201 is optimized for 2 phase single output applications up to 30A or dual output, each up to 15A with interleaved input. It includes full function PWM control, with optimized power semiconductor chip-sets and associated passives, achieving high power density. Very few external components are required to create a complete synchronous buck power supply. iPOWIR technology offers designers an innovative space-saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. IP1201 Configurations Channel 1 V IN V OUT V OUT V IN Channel 2 V OUT Single Output Dual Output * Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be applied for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The iPOWIR block will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable and reliable long term operation. See layout guidelines in datasheet for more detailed information. www.irf.com 10/6/03 1 IP1201 Parameter VIN Feedback Output Overvoltage Sense PGOOD ENABLE Soft Start Vp-ref HICCUP SYNC All specifications @ 25C (unless otherwise specified) Absolute Maximum Ratings Symbol VIN VFB1/VFB2 VFB1S/VFB2S Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 Typ Max 5.8 6 6 6 5.8 6 6 6 6 15 125 Units Conditions V SS1/SS2 HICCUP IoutVSW TBLK Output RMS Current Per Channel Block Temperature A C 2 Independent outputs. See Fig. 3 Capable of start up over full temperature range. See Note 1. Recommended Operating Conditions Parameter Input Voltage Range Symbol VIN IoutVSW Output Voltage Range VOUT 0.8 0.8 11.5 3.3 2.5 A V Min 3.14 Output RMS Current Per Channel Typ Max 5.5 15 Units A Conditions 2 Independent outputs T PCB = T CASE = 90C. See Fig. 3 2 Independent outputs T PCB = 90C, T CASE = no airflow, no heatsink. See Fig. 3 For VIN = 5V For VIN = 3.3V Electrical Specifications @ VIN = 5V Parameter Power Loss Over Current Shutdown HICCUP duty cycle Soft Start Time Reference Voltage VOUT Accuracy Error Ampifier 1 & 2 input offset voltage FB1 / FB2 Input bias current Error Amplifier source/sink Current Error Amplifier Transconductance Output Overvoltage Shutdown Threshold OVP Fault Propagation Delay PGOOD Trip Threshold PGOOD Output Low Voltage Symbol PLOSS IOC DHICCUP tSS VREF VOUT_ACC1 VOUT_ACC2 VOS1, VOS2 IB1, IB2 IERR gm1, gm2 OVP tOVP VTh_PGOOD VLo_PGOOD Min -3 -2.5 -4 Typ 6.7 20 5 5 0.80 -0.1 60 2000 1.15 x VOUT 25 0.85 x VOUT 0.25 Max 8.4 3 2.5 4 mV A A mho V s V V See OVP note in Design Guidelines Units W A % ms V % Conditions fSW = 300kHz, VIN = 5V, VOUT = 1.5V, IOUT = 15A VIN = 5V, VOUT = 1.5V, fSW = 300KHz, HICCUP pin pulled Low HICCUP pin pulled high, output short circuited. VIN = 5V, VOUT = 1.5V, CSS1 = CSS2 = 0.1F IOUT = 2A TBLK = -40C to 125C, See Note 1. VIN = 5V, VOUT = 1.5V TBLK = 0C to 125C, See Note 1. VIN = 5V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V Output forced to 1.125Vref FB1 or FB2 ramping down ISINK = 2mA 2 www.irf.com IP1201 Electrical Specifications (continued) Parameter Frequency Sync Frequency Range Sync Pulse Duration Sync, Hiccup High Level Threshold Voltage Sync, Hiccup Low Level Threshold Voltage VIN Quiescent Current Thermal Shutdown Max Duty Cycle Enable Input Logic High Enable Input Logic Low VIN Undervoltage Lockout Threshold Voltage Output Disable Soft Start Low Threshold Voltage Symbol fSW fSYNC tSYNC Min 255 480 2 IIN_Leakage Tempshdn DMAX VEN-Hi VEN-Lo VIN_UVLO VSS_Dis 90 2 Typ 200 1.0 140 2.7 Max 345 800 0.8 0.4 0.25 Units kHz kHz ns V V mA C % V V V V VIN = 5V, Enable high Conditions RT set to 30.9k Free running frequency set 20% below sync frequency fSW= 200kHz VIN = VMIN to VMAX VIN = VMIN to VMAX VIN = 5V, ENABLE Pulled Low SS1 / SS2 Pins Pulled Low Note 1: Guaranteed to meet specifications from TBLK = 0C to 90C. Specifications outside of this temperature range are guaranteed by design, and not production tested. www.irf.com 3 4 IP1201 B VCC Doubler VIN A ENABLE 25uA Bias Generator HICCUP SS1 3uA UVLO SW1 64uA Driver 1 25uA 3uA Error Amp1 R Q OC Latch / Hiccup Control VSW1 SW2 SS2 PWM Comp1 25k PWM1 0.8V 64uA 25k S FB1 CC1 Ramp1 Two phase Oscillator SYNC PGND SW3 Fig. 1: IP1201 Internal Block Diagram Error Amp2 Ramp2 PWM Comp2 Driver 2 RT VREF 0.8V VSW2 25k VP-REF PWM2 S Q R SW4 25k FB2 CC2 PGood (-10%) OVP (+15%) FB1S PGOOD www.irf.com FB2S SW1 / SW3 OFF SW2 / SW4 ON IP1201 12 11 V IN = 5V V OUT 1 = V OUT2 = 1.5V f SW = 300kHz L = 1.8H TBLK = 125C Total Power Loss, Both Outputs (W) 10 9 8 7 6 5 Maximum T ypical 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output Current Per Channel (A) Fig. 2: Power Loss vs. Current Cas e Te m pe rature (& 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 110 120 PCB Te m pe rature (C) V IN = 5V V OUT 1 = V OUT 2 = 1.5V IOUT = 15A f SW = 300kHz L = 1.8uH TX 0 10 20 30 40 50 60 70 80 90 100 110 120 Output Current Per Channel (A) Safe Operating Area www.irf.com Fig. 3: Safe Operating Area (SOA) vs. TPCB & TCASE 5 IP1201 1.030 VOU T 1 =VOU T 2 =1.5V I OU T 1 =I OU T 2 =15A 1.030 1.00 1.038 1.25 VI N =5V I OU T 1 =I OU T 2 =15A f S W =300kHz L =1.8 H T B L K =125 C 0 1.00 SOA Temp Adjustment (C) Normalized Power Loss 1.015 f S W =300k Hz L =1.8 H T B L K =125 0 C 0.50 SOA Temp Adjustment (C) Normalized Power Loss 1.023 1.015 1.008 1.000 0.993 0.985 0.978 0.970 0.5 0.75 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 1.000 0.00 0.985 - 0.50 0.970 - 1.00 0.955 - 1.50 0.940 3 3.5 4 4.5 5 5.5 - 2.00 1.0 1.5 2.0 2.5 3.0 3.5 Input V oltage (V ) Output Voltage (V) Fig. 4: Normalized Power Loss vs. VIN 1.043 1.029 1.014 1.000 0.986 0.971 0.957 0.943 0.929 0.914 0.900 200 220 240 260 280 300 320 340 360 380 400 1.50 1.00 Fig. 5: Normalized Power Loss vs. VOUT 1.048 1.60 VI N =5V 1.042 VOU T 1 =VOU T 2 =1.5V I OU T 1 =I OU T 2 =15A f S W =300k Hz T B L K =125 0 C 1.40 SOA Temp Adjustment (C) SOA Temp Adjustment (C) 0.00 -0.50 -1.00 -1.50 Normalized Power Loss Normalized Power Loss 0.50 1.036 1.030 1.024 1.018 1.012 1.006 1.000 0.994 0.0 0.5 1.0 1.5 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.20 VI N =5V VOU T 1 =VOU T 2 =1.5V I OU T 1 =I OU T 2 =15A L =1.8 H T B L K =125 0 C -2.00 -2.50 -3.00 -3.50 2.0 2.5 3.0 Sw itching Frequency (kHz) Output Inductance ( H) Fig. 6: Normalized Power Loss vs. Frequency Fig. 7: Normalized Power Loss vs. Inductance 6 www.irf.com IP1201 16 14 16 14 VI N =3.3V VI N =5.0V Load Current (A) Load Current (A) 12 10 8 6 4 2 12 10 VI N =3.3V 8 6 4 2 VI N =5.0V f S W =200k Hz 0 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 0 0.8 f S W =300k Hz 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 Output Voltage (V ) Output Voltage (V) Fig. 8: Recommended Operating Area 200kHz 16 14 12 10 8 6 4 2 f S W =400kHz 0 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 Fig. 9: Recommended Operating Area 300kHz VI N =3.3V VI N =5V Load Current (A) Output V oltage (V ) Fig. 10: Recommended Operating Area 400kHz www.irf.com 7 IP1201 Applying the Safe Operating Area (SOA) Curve The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn out through the printed circuit board and the top of the case. Case Temperature (C) Procedure 1) Draw a line from Case Temp axis at TCASE to the PCB Temp axis at TPCB. 2) Draw a vertical line from the TX axis intercept to the SOA curve. (see AN-1047 for further explanation of TX ) 3) Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y axis. The point at which the horizontal line meets the y-axis is the SOA current. 4) If no top sided heatsinking is available, assume TCASE temperature of 125C for worst case performance. Output Current (A) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 110 120 3 Safe Operating Area VIN = 5V VOUT1 = VOUT2 = 1.5V IOUT = 15A fSW = 300kHz L = 1.8uH 1 2 TX 0 10 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (C) Adjusting the Power Loss and SOA curves for different operating conditions To make adjustments to the power loss curves in Fig. 2, multiply the normalized value obtained from the curves in Figs. 4, 5, 6 or 7 by the value indicated on the power loss curve in Fig. 2. Remember that the power loss in Fig 2. is the power loss for 2 outputs operating with the same output voltage. If differing output voltages are used the initial power loss for each channel needs to be divided by 2. Then if multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 2. The resulting product is the final power loss based on all factors. See example no. 1. To make adjustments to the SOA curve in Fig. 3, determine your maximum PCB Temp & Case Temp at the maximum operating current of each IP1201. Then, add the correction temperature from the normalized curves in Figs. 4, 5, 6 or 7 to the TX axis intercept (see procedure no. 2 above) in Fig. 3. When multiple adjustments are required, add all of the temperatures together, then add the sum to the TX axis intercept in Fig. 3. See example no. 2. Note: First check Fig. 8, Fig. 9 or Fig. 10 for maximum current capability Operating Conditions for the following examples: Output1 Output Current = 10A Input Voltage = 3.3V Output Voltage = 1.5V Sw Freq= 200kHz Output2 Output Current = 13A Output Voltage = 1.0V Input Voltage =3.3V Sw Freq= 200kHz Inductor = 1.75H Inductor = 1.75H Example 1) Adjusting for Maximum Power Loss: Output1 (Fig. 2) Maximum power loss = 5.3W /2 = 2.65W (Fig. 4) Normalized power loss for input voltage 0.97 (Fig. 5) Normalized power loss for output voltage 1.0 (Fig. 6) Normalized power loss for frequency 0.918 (Fig. 7) Normalized power loss for inductor value 1.0 Adjusted Power Loss = 2.65W x 0.97 x 1.0 x 0.918 x 1.0 2.36W 8 www.irf.com IP1201 Output2 (Fig. 2) (Fig. 4) (Fig. 5) (Fig. 6) (Fig. 7) Maximum power loss = 8.25W /2 = 4.13W Normalized power loss for input voltage 0.97 Normalized power loss for output voltage 0.98 Normalized power loss for frequency 0.918 Normalized power loss for inductor value 1.0 Adjusted Power Loss = 4.13W x 0.97 x 0.98 x 0.918 x 1.0 3.60W Total device power loss = 2.36W + 3.60W = 5.96W Example 2) Adjusting for SOA Temperature: Assuming TCASE = 110C & TPCB = 90C for both outputs Output1 (Fig. 4) Normalized SOA Temperature for input voltage -1.0C (Fig. 5) Normalized SOA Temperature for output voltage 0C (Fig. 6) Normalized SOA Temperature for frequency -2.9C (Fig. 7) Normalized SOA Temperature for inductor value 0C TX axis intercept temp adjustment = -1.0C + 0C -2.9C + 0C -3.9C The following example shows how the SOA current is adjusted for a TX change of -3.9C and output 1 is in SOA Case Temperature (C) 16 15 14 13 12 11 Output Current (A) 0 10 20 30 40 50 60 70 80 90 100 110 120 Adjusted SOA Current Unadjusted SOA Current 10 9 8 7 6 5 4 3 2 1 0 0 10 Safe Operating Area TX VIN = 5V VOUT1 = VOUT2 = 1.5V IOUT = 15A fSW = 300kHz L = 1.8uH 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (C) Output2 (Fig. 4) (Fig. 5) (Fig. 6) (Fig. 7) Normalized SOA Temperature for input voltage -1.0C Normalized SOA Temperature for output voltage -0.55C Normalized SOA Temperature for frequency -2.9C Normalized SOA Temperature for inductor value 0C TX axis intercept temp adjustment = -1.0C - 0.55C - 2.9C + 0C -4.45C The following example shows how the SOA current is adjusted for a TX change of -4.45C and output 2 is in SOA. Case Temperature (C) 50 60 70 16 15 14 13 12 11 0 10 20 30 40 80 90 100 110 120 Adjusted SOA Unadjusted SOA Output Current (A) 10 9 8 7 6 5 4 3 2 1 0 0 10 Safe Operating Area TX VIN = 5V VOUT1 = VOUT2 = 1.5V IOUT = 15A fSW = 300kHz L = 1.8uH 20 30 40 50 60 70 80 90 100 110 120 PCB Temperature (C) www.irf.com 9 IP1201 Pin Name VIN A* B* CC1 CC2 ENABLE SS1 SS2 FB1 FB1s FB2 FB2s VSW1 VSW2 Ball Designator A1 A2 A3 A4 A5 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C14 C15 C16 C17 C18 G8 J13 L12 L13 H8 H13 A8 B8 H6 G11 J6 J8 H11 J11 D1 D2 D3 E1 E2 F1 F2 G1 G2 G3 H1 H2 H3 J1 J2 J3 K1 K2 L1 L2 D16 D17 D18 E17 E18 F17 F18 G16 G17 G18 H16 H17 H18 J16 J17 J18 K17 K18 L17 L18 A6 A7 A9 A10 A12 A13 B6 B7 B9 B10 B12 B13 C6 C7 C9 C10 C12 C13 D6 D7 D9 D10 D12 D13 D14 E3 E4 E8 E11 E15 E16 F3 F4 F5 F6 F9 F10 F13 F14 F15 F16 G4 G5 G6 G9 G10 G13 G14 G15 H4 H5 H9 H10 H14 H15 J4 J5 J9 J10 J14 J15 K3 K16 L3 L5 L14 L16 L9 L8 K6 K13 L10 L6 L7 L11 Pin Description Input voltage connection node Internally generated voltage. Connect to pin B when Vin < 3.5V. Leave floating for input voltages >3.5V. Internally generated voltage. Connect to pin A when Vin < 3.5V. Leave floating for input voltages >3.5V. Output of the first error amplifier, refer to Fig.1 block diagram Output of the second error amplifier Single pin for both outputs. Commands outputs ON or OFF. Pulled low, turns both outputs ON. Should be pulled high to disable outputs. Soft start pin for output1. External capacitor provides soft start. Pulled low disables output 1. Soft start pin for output2. External capacitor provides soft start. Pulled low disables output 2. Inverting input of error amplifier 1 Output 1 voltage sense pin Inverting input of error amplifier 2 Output 2 voltage sense pin Output 1 inductor connection node Output 2 inductor connection node PGND Power Ground Vref VP-ref SYNC RT PGOOD HICCUP NC Amplifier 1 reference Voltage. Connect a 100pf cap from this pin to PGND. Amplifier 2 reference voltage. Connect to Vref for independent output configuration. Refer to function description section on how to connect for parallel configuration. External Clock synchronization pin. Set free running frequency to 80% of the SYNC frequency. When not in use leave pin floating. Switching frequency setting pin. For RT selection, refer to Fig.11 RT vs Frequency curve. Power Good pin, needs external pull-up resistor. If not used pin can be left floating. Logic level pin. Pulled high enables hiccup mode of operation. Pulled low enables overcurrent shutdown mode. Unused pin. No electrical connection. * Part will malfunction if pins A and B are shorted together for input voltages >3.5V Table 1: Pin Description 10 www.irf.com IP1201 400 Switching Frequency in kHz 380 360 340 320 300 280 260 240 220 200 20 25 30 35 40 45 50 RT in kOhms Fig. 11: Per Channel Switching Frequency vs RT Iin Average A V Vin Average Cin Vin DC PIN = VIN Average x IIN Average POUT = (VOUT1 Average x IOUT1 Average) + + (VOUT2 Average x IOUT2 Average) PLOSS = PIN - POUT Iout1 Average VI N Lo1 VSW1 A Vout1 Iout1 Co1 FB1 IP1201 FB2 Averaging Circuit 1 V Vout1 Average Iout2 Average Lo2 SGND PGND VSW2 A Vout2 Iout2 Co2 Averaging Circuit 2 V Vout2 Average Fig. 12: Power Loss Test Circuit www.irf.com 11 IP1201 ENABLE VIN VIN PGND PGND VSW1 A SS1 CC1 FB1 FB1s SYNC Vref SS2 CC2 FB2 A FB2s RT NC B VSW2 HICCUP VP-ref PGOOD All Dimensions in inches (millimeters) Fig. 13: Recommended PCB Footprint (Top View) 12 www.irf.com IP1201 IP1201 Users Design Guidelines The IP1201 can be configured as a dual channel 15A or parallel single 30A power block consisting of optimized power semiconductors, PWM control and its associated passive components. It is based on a synchronous buck topology and offers an optimized solution where space, efficiency and noise caused by parasitics are of concern. The phase shifted, two output power block operates with fixed frequency voltage mode control and can be configured to operate as a dual output or paralleled single output with current sharing. The IP1201 components are integrated in a ball grid array (BGA) package. VIN The input operating voltage range of the IP1201 is 3.14V to 5.5V. Both channels of the power block have a common input. For applications where the input bus voltage is less than 3.5V, A and B pins should be shorted. For input voltages greater than 3.5V, A and B pins should be disconnected and floating. Voltages at A and B pins are internally generated, no external voltage source should be connected to either one of these pins. A Power-On-Reset is performed when VIN falls below 2.5V. Enabling the Outputs The ENABLE pin turns on and turns off both outputs of the IP1201 simultaneously. The IP1201 outputs will be turned off by pulling the ENABLE pin to VIN. ENABLE low will start the outputs. The converter can also be shutdown by pulling the soft-start pins to PGND through a logic level MOSFET the drain of which connects to the soft start pin (see Fig.14). This feature can be useful if sequencing or different start-up timing of the outputs are required. In situations where the output has undergone a latched shutdown due to overvoltage or overcurrent, cycling ENABLE will reset the outputs. Cycling soft start pins will not unlatch the outputs. Dual Soft Start The Soft Start function provides a controlled rise of the output voltage, thus limiting the inrush current during start-up. The IP1201 provides two independent soft start functions. The soft start pins can be connected to the soft start capacitors to provide www.irf.com VCss VOUT Iss SS1/SS2 Css IP1201 Fig. 14: Soft Start/Enable Circuit different start-up and sequencing profiles. Each soft start function has an internal 25uA +/-20% current source that charges the external soft start capacitor Css up to 3V. During power-up, the output voltage starts ramping up only after the charging voltage across the C ss capacitor has reached a 0.8Vtyp threshold, as shown in Fig. 15. 3V 0.8Vtyp Fig. 15: Power Up Threshold This threshold voltage should be taken into consideration when designing sequencing profiles using the IP1201 as it will effect start-up delays and ramptimes. To ensure complete discharge of the soft start capacitor Css, it is recommended to add a 1M resistor directly across Css. For proper implementation of sequencing of outputs using the IP1201, refer to IR Application Note AN-1053 - Power sequencing techniques using IP1201 and iP1202. 13 IP1201 Mode of Operation The IP1201 can be configured to provide either two independent dual outputs or single paralleled output with current share. In dual output mode, the two error amplifiers of the PWM controller operate independently. Each output voltage of the IP1201 block is controlled by its own error amplifier. The output of the error amplifier and the internally generated ramp signal are compared to produce PWM pulses of fixed frequency that drive the internal power switches. In this mode, the VP-ref pin must be connected to Vref pin. Vref pin is the internally generated 0.8V reference input of first error amplifier . Refer to the internal block diagram of the IP1201 in Fig.1. In single output mode, one error amplifier controls the output voltage and the other amplifier monitors the inductor current information for current sharing. In this mode, VP-ref pin must be disconnected from Vref pin and connected to the output of the inductor. See Fig. 16. The inductor current information is provided through external shunts placed in series with the output inductors. A lossless inductor current sensing scheme can also be implemented as shown in Fig. 17 where the current is sensed throughthe DC resistance of the inductor. The IP1201 can also be configured in dual output tracking mode where the second output tracks the first output. For a specific output configuration, follow the connection diagram shown in Fig.16, Fig.17 and Fig.18 at the end of this section. Out of Phase Operation The dual output PWM controller inside the IP1201 provides a 180 out of phase operation of the PWM outputs. This method of control offers the advantage of reducing the amount of input bypass capacitors due to increase in input ripple frequency and hence reduction of ripple amplitude. Moreover, for paralleled output configurations 180 phase shifting contributes to smaller output capacitors due to output inductor ripple current cancellation and ripple reduction. Frequency and Synchronization The operating switching frequency (fSW) range of 14 IP1201 is 200 kHz to 400 kHz. The desired frequency is set by placing an external resistor to the RT pin of the IP1201. See Fig. 11 for the proper resistor value. The IP1201 is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge clock. The free running oscillator frequency is twice the per-channel frequency. During synchronization, RT is selected such that the free running frequency is 20% below the synchronization frequency. The maximum synchronization frequency that IP1201 can accept is 800kHz. Note that the actual free running frequency of individual output is half the synchronization frequency. Synchronization capability is provided both in independent and parallel configurations. When unused, the SYNC pin must be left floating. Overcurrent Protection/Autorestart The Overcurrent Protection function of the IP1201 offers two distinct modes: HICCUP of the output and Overcurrent Shutdown. If the Hiccup pin is pulled high (Hiccup enabled), hiccup mode will be selected. If Hiccup pin is pulled low (Hiccup disabled), overcurrent shutdown will be selected. During overloads, in HICCUP disabled mode, the controller shuts down as soon as the trip threshold is reached. In HICCUP enabled mode, when overcurrent trip threshold is reached, the power supply output shuts down and attempts to restart. The time duration between the shutdown of the output and the restart is determined by the time it takes to discharge the soft start capacitor. Typically, the discharge time of the soft start capacitor is 10 times the charge time. The duty cycle of the hiccup process is typically 5%.The output will stay in hiccup indefinitely until the overload is removed. The typical overcurrent trip threshold of the device is internally set at 20A. Overvoltage Protection (OVP) Overvoltage is sensed through separate output voltage sense pins FB1s and FB2s. A separate OVP circuit is provided for each output and the OVP threshold is set to 115% of the output voltage. Upon overvoltage condition of either one of the outputs, the OVP forces a latched shutdown on both outputs. In this mode, the upper FETs turn off and the lower FETs turn on, thus crowbaring the outputs. Reset is performed by recycling the ENABLE pin. www.irf.com IP1201 Overvoltage can be sensed by either connecting FB1s and FB2s to their corresponding outputs through separate output voltage divider resistor networks, or they can be connected directly to their corrsponding feedback pins FB1 and FB2. For Type III control loop compensation, FB1s and FB2s should be connected through separate voltage dividers only. PGOOD This is an output voltage status signal that is open collector and is pulled low when the output voltage falls below 85% of the outout voltage. High state indicates that outputs are in regulation. There is only one PGOOD for both outputs. The PGOOD pin can be left floating if not used. Thermal Shutdown The IP1201 provides thermal shutdown. The threshold typically is set to 140C. When the trip threshold is exceeded, thermal shutdown turns the outputs off. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to the normal range. C18 1uF VIN B A VIN VSW1 FB1 L1 Cin 100uF x4 R1 100k C9 CC1 VOUT1 1.5V R9 887 Cout1 470uF x2 1.0uH HICCUP FB1S R7 1k 0.01uF R2 100k SS1 PGOOD R5 4.75k C8 0.1uF VP-REF IP1201 SS2 VREF 0.8V C10 100pF L2 C7 0.1uF R24 100k VOUT2 2.5V R10 Cout2 470uF x2 VSW2 1.0uH ENABLE FB2 2.15k FB2S C11 CC2 R8 1k R6 7.15k R3 30.9k SYNC PGND RT 6800pF PGND Fig. 16: IP1201 Dual Output Simplified Schematic www.irf.com 15 IP1201 C18 1uF VIN B A VIN VSW1 L1 Cin 100uF x4 R1 100k HICCUP FB1S CC1 Rshunt1 5mOhm VOUT 1.5V Cout 470uF x4 1.0uH R9 FB1 887 R7 1k C9 0.01uF R5 4.75k R2 100k PGOOD SS1 C8 0.1uF VP-REF IP1201 SS2 VREF 0.8V C10 100pF L2 C7 0.1uF R24 100k ENABLE VSW2 FB2 FB2S CC2 Rshunt2 5mOHM 1.0uH C11 6800pF R6 7.15k R3 30.9k SYNC PGND Fig. 17: IP1201 Single Output Simplified Schematic C18 1uF VIN B A VIN VSW1 PGND RT L1 1.0uH RL1 1.0k FB1 VOUT 1.5V CL1 1.0uF R9 887 Cout 470uF x4 Cin 100uF x4 R1 100k FB1S CC1 HICCUP C9 0.01uF R5 4.75k R7 1k R2 100k PGOOD SS1 R13 887 C8 0.1uF VP-REF IP1201 SS2 VREF R14 1k 0.8V C10 100pF L2 C7 0.1uF R24 100k ENABLE VSW2 1.0uH RL2 1.0k CL2 1.0uF FB2 R3 30.9k PGND RT SYNC FB2S CC2 C11 6800pF R6 7.15k PGND Fig. 18: IP1201 Single Output Lossless Inductor Current Sensing Simplified Schematic 16 www.irf.com IP1201 IP1201 Design Procedure Only a few external components are required to complete a dual output synchronous buck power supply using IP1201. The following procedure will guide the designer through the design and selection process of these external components. A typical application for IP1201 will be: VIN = 3.3V, VOUT1 = 1.5V, IOUT1 = 10A, VOUT2 = 2.5V, IOUT2 = 6A, fsw = 200kHz, Vp-p1 = Vp-p2 = 40mV Setting the Output Voltage The output voltage of the IP1201 is set by the 0.8V reference Vref and external voltage dividers. Vout1 nal reference source to VP-ref. In this case, to ensure proper start-up, power to VP-ref and IP1201 must be applied simultaneuosly. Setting the Overvoltage Trip Both outputs of the IP1201 will shut down if either one of the outputs experiences a voltage in the range of 115% of VOUT. The overvoltage sense pins FB1s and FB2s are connected to the output through voltage dividers, R13 and R14 (Fig. 19), and the trip setpoints are programmed according to equation (1). Separate overvoltage sense pins FB1s and FB2s are provided to protect the power supply output if for some reason the main feedback loop is lost (for instance, loss of feedback resistors). If this redundancy is not required and if Type II control loop compensation scheme is utilized, FB1s and FB2s pins can be connected to FB1 and FB2 pins respectively. An optional 100pF capacitor (C26) is used for delay and filtering purposes. Setting the Soft-Start Capacitor R 9 FB1 R 7 IP1201 R 13 FB1S The soft start capacitor Css is selected according to equation (2): tss = 40 x Css (2) C 26 (Optional) R 14 where, tss is the output voltage ramp time in milliseconds, and Css is the soft start capacitor in F. A 0.1F capacitor will provide an output voltage rampup time of about 4ms. Fig. 19: Typical scheme for output voltage setting VOUT1 is set according to equation (1): VOUT1 = Vref x (1 + R9 /R7 ) (see Fig. 19) (1) Input Capacitor Selection The switching currents impose RMS current requirements on the input capacitors. The expression in equation (3) allows the selection of the input capacitors: Setting R7 to 1K, VOUT1 to 1.5V and Vref to 0.8V, will result in R9= 875 ohms (select 887 ohms). Final values can be selected according to the desired accuracy of the output. If the 0.8V reference is used to set the voltage for the second output VOUT2, VP-ref pin must be shorted to Vref pin and in a similar way, voltage divider resistors are selected for the second output VOUT2. The second output can also be set by applying an exterwww.irf.com I RMS =I LOAD x D(1 - D) where, D is the duty cycle and is expressed as: D = VOUT / VIN. (3) For output1 of the above example D= 0.45 and, IRMS = 10 x SQRT (0.45(1-0.45)) = 5A For output2 of the above example D = 0.75 and, 17 IP1201 IRMS = 6 x SQRT (0.75(1 - 0.75)) = 2.6A For better efficiency and low input ripple, select low ESR ceramic capacitors. The amount of the capacitors is determined based on the r.m.s. rating. In the above example, a total of 3 x 100F, 3.5A capacitors will be required to support the input r.m.s. current (see the parts list in the reference design section of this datasheet). The 180 out of phase operation of the IP1201 provides reduced voltage ripple at the input of the device. This reduction in ripple requires less input bypass capacitance. Therefore the input bypass capacitor selection criteria based on equation (3) provides a worst case solution for the selected operating conditions. Output Capacitor CO Selection Selection of the output capacitors depends on two factors: a. Low effective ESR for ripple and load transient requirements To support the load transients and to stay within a specified voltage dip V due to the transients, e.s.r. selection should satisfy equation (4): Resr V / ILoadmax Where, ILoadmax is the maximum load current. If output voltage ripple is required to be maintained at specified levels then, the expression in equation (5) should be used to select the output capacitors. Resr Vp-p / Iripple (5) (4) properly compensate the control loop for low output capacitor e.s.r. values. When selecting output capacitors, it is important to consider the overshoot performance of the power supply. If the amount of capacitance is not adequate, then, when unloading the output, the magnitude of the overshoot due to stored inductor energy, and depending on the speed of the response of the control loop, can exceed the overvoltage trip threshold of the IP1201 and can cause undesirable shutdown of the output. The magnitude of the overshoot should be kept below 1.125VOUT . To prevent the overshoot from tripping the output a delay can be added by installing capacitor C26 as shown in Fig.19. In paralleled single output configuration, due to 180 phase shift, the peak to peak output voltage ripple will be reduced because of doubling of the ripple frequency. Also, the resulting ripple current in the output capacitors will be smaller than the ripple current of each channel. There is some cancellation effect of these current, the magnitude of which depends on the duty cycle. b. Stability The value of the output capacitor e.s.r. zero frequency fesr plays a major role in determining stability. fesr is calculated by the expression in equation (6). fesr = 1 / (2 x Resr x CO) (6) Details on how to consider this parameter to design for stability will be outlined in the control loop compensation section of this datasheet. Inductor LO Selection Inductor selection is based on trade-offs between size and efficiency. Low inductor values result in smaller sizes, but can cause large ripple currents and lower efficiency. Low inductor values also benefit the transient performance. The inductor Lois selected according to equation (7): LO = Vout x (1 - D) / (fsw x Iripple) (7) Where, Vp-p is the single phase peak to peak output voltage ripple. Iripple is the inductor current peak-to peak ripple. If the inductor current ripple Iripple is 30% of IOUT1, the 40mV peak to peak output voltage ripple requirement will be met if the total e.s.r. of the output capacitors is less than 11mohms. This will require 3 x 470F POSCAP capacitors (See the parts list in the reference design section of this datasheet). Additional ceramic capacitors can be added in parallel to further reduce the e.s.r. Care should be given to 18 For output 1 of the above example, and for Iripple of 30% of IOUT1, LO1 is calculated to be 1.1H. The core must be selected according to the peak of maximum output current. A similar calculation can be applied to find an inducwww.irf.com IP1201 tor value for the second output. Magnitude(dB) Control Loop Compensation The IP1201 feedback control is based on single loop voltage mode control principle if both outputs are configured in dual output independent mode. In this case, both outputs can have identical compensation. If IP1201 outputs are configured for parallel operation, then compensation of the outputs will differ slightly. The goal in the design of the compensator is to achieve the highest unity gain (0 db) crossover frequency with sufficient phase margin for the closed loop transfer function. The LC filter of the power supply introduces a double pole with 40db/dec slope and 1800 phase lag. The 180 phase contribution from the LC filter is the source of instabilty. The resonant frequency of the LC filter is expressed by equation (8): H(s) dB FZ Frequency Fig. 20: Typical Type II compensation and its gain plot From Fig.19 the transfer function H(s) of the error amplifier is given by (9): R7 1 + sR5 C9 (9) x R7 + R9 sC 9 R5 The term s represents the frequency dependence of the transfer function. H ( s) = g m x The Type II controller introduces a gain and a zero expressed by equations (10) and (11): H (s) = g m x R7 x R5 R7 + R9 f LC = 1 / (2 L0 x C 0 ) (8) (10) The error amplifiers of the IP1201 PWM controller are transconductance amplifiers, and their outputs are available for external compensation. Two type of compensators are studied in this section. The first one is called Type II and it is used to compensate systems the e.s.r. frequency fesr (equation 6) of which is in the midfrequency range and Type III that can be used for any type of output capacitors and have a wide range of fesr. Type II Vout1 where, gm is the transconductance of the error amplifier. fz = 1 2 x R5 x C 9 (11) Follow the steps below to determine the feedback loop compensation component values: 1. Select a zero db crossover frequency f0 in the range of 10% to 20% of the switching frequency fsw. 2. Calculate R5 using equation (12): R 9 FB1 R 7 IP1201 R5 = 1.25 x f xf R + R9 1 1 x 0 2esr x 7 x VIN R7 gm f LC (12) E/A1 VREF C 10 Ve C 9 C C1 (Optional) Where, VIN = Maximum Input voltage f0 = Error amplifier zero crossover frequency fesr= Output capacitor Co zero frequency fLC = Output frequency resonant filter g m = Error amplifier transconductance. Use 2000mho for gm. R 5 www.irf.com 19 IP1201 3. Place a zero at 75% of fLC to cancel one of the LC filter poles. Vout1 C 22 C 9 f z = 0 . 75 x 1 2 Lo x C o R 26 (13) C 21 C C1 R 25 R 9 FB1 R 7 VREF E/A1 4. Calculate C9 using equations (11) and (13) Calculation of compensation components for output1, based on the example above yields: fLC = 4.0kHz fz = 3.0kHz f0 = 20kHz (based on Fsw = 200kHz) fesr = 10kHz, per equation (7) using Resr = 11m. R5 = 4.5K C9 = 12nF The same steps can be used to determine the values of the compensation components for output2. Sometimes, a pole fp2 is added at half the switching frequency to filter the switching noise. This is done by adding a capacitor Copt in Fig.20 from the output of the error amplifier (CC pin of IP1201) to ground. This pole is given by equation (14): IP1201 C 10 Magnitude(dB) H(s) dB FZ1 FZ2 FP2 FP3 Frequency Fig. 21: Typical Type III compensation and its gain plot The frequencies of the three poles and the two zeros of the type III compensation scheme are represented by the following equations: fp1= 0 (17) f p2 1 2 x R5 x Copt (14) Select Copt such that: Copt C9 10 (15) Type III Type III compensation scheme allows the use of any type of capacitors with esr frequency of any range. This scheme suggests a double pole double zero compensation and requires more components around the error amplifier to achieve the desired gain and phase margins. Fig. 21 represents the type III compensation network for IP1201. The transfer function of the type III compensator is given by eqaution (16) f p2 = 1 2 x R2 5 x C 21 1 2 x R2 6 x C 22 (18) f p3 (19) f z1 = 1 2 x R26 x C9 (20) 1 (1 + sR26C 9 ) x (1 + sR9C21 ) H (s) x sR9C9 (1 + sR 26 C22 ) x (1 + sR25C21 ) 20 f z2 = (16) 1 2 x R9 x C 21 (21) www.irf.com IP1201 The crossover frequency f0 for type III compensation is represented by equation (22): sensing shunts for the same outputs. Vsw1 f 0 = 0.8 x Vin x R26 x C 21 x 1 2 x Lo x C o (22) L1 Follow the steps below to determine the feedback loop compensation component values: 1. Select a zero db crossover frequency f0 in the range of 10% to 20% of the switching frequency fsw. 2. Select R26 = ~1k 3. Place the first zero fz1 at 75% of the resonant frequency fLC of the output filter. Determine C9 from equation (20). 4. Select C22 such that C 22 IP1201 Vp-R ef Rsh1 VOUT E/A2 FB2 C C2 Rsh2 C 11 L2 R 6 Vsw2 RLoad C9 10 Doing so will place a third pole fP3 at or near half the switching frequency fSW. 5. Calculate C21 from equation (22). 6. Place the second pole fp2 at fesr of the output capacitor Co and determine the value of R25 from equation (18). 7. Place the second zero near the resonant frequency fLC of the output filter. Calculate R9 using equation (21). 8. Use equation (1) to calculate R7. More than one iteration may be required to calculate the values of the compensation components if crossover frequencies higher than the range specified in step 1 are required (for higher bandwidths and faster transient response performance). To ensure stability a phase margin greater than 45 should be achieved. If the IP1201 is configured in single output paralleled configuration, the feedback loop of the first output is closed around the output voltage, and the second amplifier, which is also a transconductance one, forces equal sharing of the inductor currents in both outputs. In Fig. 22, L1 and L2 are the inductors for outputs 1 and 2 respectively. Rsh1 and Rsh2 are the current www.irf.com Fig. 22: Output 2 error amplifier compensation network for parallel configuration. For type II compensation scheme resistor R6 is calculated according to equation (23) R6 = 1.25 x 2 x f 02 xL 2 1 x g m x Rsh1 Vin - Vout (23) where, f02 is the desired zero crossover frequency. The zero frequency fz of the compensation network is expressed in equation (24) fz = 1 2 x R6 x C11 (24) and should be placed near half the output2 resonant frequency fLC2. fz = f LC 2 2 (25) A value for C11 is calculated by using equations (23), (24) and (25). 21 IP1201 Typical Waveforms Ch1 Ch3 Ch2 Ch4 Ch1: Output 1 switching node, 400kHz Ch2: Output 2 switching node, 400kHz Ch4: 800kHz external synchronization Ch1: Ch2: Ch3: Ch4: Output Output Output Output 1 voltage, 1V/div 2 voltage, 1V/div 1 load current, 10A/div 2 load current, 10A/div Fig. 23: IP1201 Outputs synchronized to 800kHz Fig. 24: IP1201 hiccup response (Output 1 hiccups due to overload, whereas Output 2 continues uniterrupted) Ch1: Output voltage, 50mV/div ac Ch3: Load current, 5A/div Ch1: Output voltage, 20mV/div ac Ch3: Load current, 5A/div Fig. 25: IP1201 Transient response load step 1A to 12A 22 Fig. 26: IP1201 Transient response load step 12A to 0A www.irf.com IP1201 Ch1 Ch3 Ch2 Ch4 Ch1: Ch2: Ch3: Ch4: Output Output Output Output 1 voltage, 1V/div 2 voltage, 1V/div 1 load current, 10A/div 2 load current, 10A/div Fig. 27: IP1201 latched overcurrent response (output1 shutsdown due to overload, whereas output2 continues uninterrupted) Vin=3.3V Ch1: Output Ch2: Output Ch3: Output Ch4: Output 1 switch node voltage 5V/div 2 switch node voltage 5V/div 1 inductor current, 5A/div 2 inductor current , 5A/div Fig. 28: IP1201 inductor current sharing Ch1: Output1 voltage, 1V/div Ch2: Output2 voltage, 1V/div Vin=5V Ch1: Output 1 switch node voltage 5V/div Ch2: Output 2 switch node voltage 5V/div Ch3: Output voltage ripple, 10mV/div Fig. 29: IP1201 overvoltage trip. (Overvoltage on output2 causes both outputs to shutdown) www.irf.com Fig. 30: IP1201 Output voltage ripple in parallel configuration 23 IP1201 Ch1: Output 1, 0.5V/div Ch2: Output 2, 0.5V/div Ch1: Output 1, 0.5V/div Ch2: Output 2, 0.5V/div Fig. 31: IP1201 output sequencing with separate soft-start capacitors Fig. 32: IP1201 output sequencing with separate soft-start capacitor and delayed turn-on 24 www.irf.com IP1201 Layout Guidelines For stable and noise free operation of the whole power system, it is recommended that the designer uses the following guidelines: 1. Follow the layout scheme presented in Fig. 33. Make sure that the output inductors L1 and L2 are placed as close to IP1201 as possible to prevent noise propagation that can be caused by switching of power at the switching node Vsw, to sensitive circuits. 2. Provide a mid-layer solid ground plane with connections to the top layer through vias. The PGND pads of IP1201 also need to be connected to the same ground plane through vias. 3. To increase power supply noise immunity, place input and output capacitors close to one another, as shown in the layout diagram. This will provide short high current paths that are essential at the ground terminals. 4. Although there is a certain degree of VIN bypassing inside the IP1201, the external input decoupling capacitors should be as close to the device as possible. 5. The Feedback tracks from the outputs VOUT1 and VOUT2 to FB1 and FB2 respectively, should be routed as far away from noise generating traces as possible. 6. The compensation components and the Vref bypass capacitor should be placed as close as possible to their corresponding IP1201 pins. 7. For single output configuration, the parasitic paths leading to the common output connector from each parallel branch should be symmetrically routed to ensure equal current sharing. 8. Refer to IR application note AN-1029 to determine what size vias and copper weight and thickness to use when designing the PCB. Fig. 33: IP1201 suggested layout www.irf.com 25 B A VSW1S VSW1S PG NDS 1 2 2 R1 0 Installed Re moved SYNC PGND Fig. 34: Reference Design Schematic CC1 1 26 IP1201 JP1-1 JP2-1 JP3-1 *For Vin < 3.5V, short A & B through JP2 jumper. *For Vin > 3.5V, remove jumper JP2. B 1 2 TP3 C18 1uF (Optional) VSW1S SHUNT JP2 * A/B VIN VS W1 SHUNT SHUNT A VIN TP1 VIN VSW1 1.0uH FB1 887 1% 6.3 V 6.3V TP28 VIN TP8 VSW1 L1 R15 5mOHM (short f r independent o output configuration) C12 470uF C13 470uF C25 NI VO UT1 (1.5V) TP VO VIN VIN=3.14V-5.5V C4 100uF 6.3V R9** FB1 TP2 C1 100uF 6.3V C2 100uF 6.3V C3 100uF 6.3V C5 100uF 6.3V C6 100uF 6.3V PGND R25 NI R7** 1K 1% C21 NI C14 0.1uF TP4 C22 NI VIN HICCUP TP29 PGND R26 NI C9 0.01uF R5 4.75K PGND R1 HICCUP CC1 100K JP1 HICCUP FB 1S CON4 1 2 ENABLE VINS TP PG 3 4 5 6 VSW1S FB1S 887 1% C19 100pF R14 1K 1% R13 7 8 VSW2S 9 10 VOUT1 PGOOD VP -REF VIN PGOOD VP-REF R4 0 SS1 SS1 VREF R2 100K R16 0 11 12 VOUT2 13 14 R23 0 15 16 VREF C10 100pF VS W2S 0.8V INPUT/OUTPUT C8 0.1uF VSW2S IP1201 TYPE III Compensation TP10 VSW2 SS2 SS2 VS W2 Compensation Configuration VSW2 L2 1.0uH TP VO R19 5mOHM o R17 (short f r independent 0 output configuration) FB2 VO UT2 De signa tor Typ II Configuratio e n Typ III Configuratio e n (2.5V) R25, R2 R2 R28 6, 7, Re moved Installed C2 C23 1, Re moved Installed C7 0.1uF VIN FB2 C2 C24 2, Re moved Installed C9 C11 , Installed Installed R10 2.15k 1% C24 NI R28 NI R27 C23 NI NI R8 1k 1% C11 6800pF FB1S R22 0 R6 7.15k C15 470uF 6.3V C16 470uF 6.3 V C26 NI C17 0.1uF R5 R6 , Installed Re moved R24 100K ENABLE ENABLE CC2 Output Configuration JP3 ENABLE CC2 TP PG De signator Ind epend m ent ode(dual o utput) 2p hasemode (single outp ut) R15, R1 9 Short 5m OHM R3 RT RT FB 2S FB2S R11 2.15K 1% R1 6 Removed Installed 30.9K C20 100pF R12 1K 1% R1 7 Removed Installed **For independent mode, output voltages are set by using the following equations: For VOUT1: R9 = R7[(VOUT1/V REF) - 1]. For VOUT2: R10 = R8[(V OUT2/VREF) - 1]. Set R7 (or R8) to 1K, V REF to 0.8V, and VOUT to desired output, then solve for R9 (or R10 respectively). For parallel (single output) mode, check table on the left. R8 Installed Re moved TP6 SYNC SYNC R4 Installed Re moved R1 R12 1 Installed Re moved R2 2 Re moved Installed R2 3 Re moved Installed (Shorted) www.irf.com IP1201 IRDCIP1201-A (Dual, Independent output configurations(Channel1 1.5V output, Channel2 2.5V output) QTY 6 3 1 4 4 1 14 1 2 3 2 4 2 2 1 1 1 1 1 REF DESIGNATOR C1, C2, C3, C4, C5, C6 C10, C19,C20 C11 C12, C13, C15, C16 C14, C17, C7, C8 C18 C21, C22, C23, C24, C25, C26, R16, R17, R22, R23, R25, R26, R27, R28 C9 L1, L2 R1, R2, R24 R10, R11 R12, R14, R7, R8 R13, R9 R15, R19 R3 R4 R5 R6 U1 DESCRIPTION Capacitor, ceramic, 100F, 6.3V, X5R, 20% Capacitor, ceramic, 100pF, 50V, NPO, 5% Capacitor, ceramic, 6800pF, 50V, X7R, 10% Capacitor, poscap, 470F, 6.3V, electrolytic 20% Capacitor, ceramic, 0.1F, 16V, X7R, 10% Capacitor, ceramic, 1.00F, 16V, X7R, 10% Not installed Capacitor, ceramic, 0.01F, 50V, X7R, 10% Inductor, 1H, 19A, 20% Resistor, thick film, 100k, 1/10W, 1% Resistor, thick film, 2.15k, 1/10W, 1% Resistor, thick film, 1.0k, 1/10W, 1% Resistor, thick film, 887, 1/10W, 1% Resistor, manganin-foil, 0, 2W Resistor, thick film, 30.9k, 1/10W, 1% Resistor, thick film, 0, 1/10W Resistor, thick film, 4.75k, 1/10W, 1% Resistor, thick film, 7.15k, 1/10W, 1% BGA Power Block SIZE 1812 0603 0603 7343 0603 0805 0603 13.0mm X 12.9mm 0603 0603 0603 0603 2716 0603 0603 0603 0603 9.25mm X 15.5mm MFR TDK Phycomp KOA Sanyo Murata Murata Samsung Panasonic KOA KOA KOA KOA Isotek Corp KOA ROHM KOA KOA IR PART NUMBER C4532X5R0J107M 0603CG101J9B20 X7R0603HTTD682K 6TPB470M GRM188R71C104KA01D GRM40X7R105K016 CL10B103KBNC ETQP1H1R0BFA RK73H1J1003F RK73H1J2151F RK73H1J1001F RK73H1J8870F SMT-R000 RK73H1J3092F MCR03EZHJ000 RK73H1JLTD4751F RK73H1JLTD7151F IP1201 IRDCIP1201-A (Single, paralleled output configuration(for 1.5V output) QTY 6 3 1 4 4 1 15 1 2 3 2 2 2 1 1 3 1 1 1 REF DESIGNATOR C1, C2, C3, C4, C5, C6 C10, C19,C20 C11 C12, C13, C15, C16 C14, C17, C7, C8 C18 C21, C22, C23, C24, C25, C26, R10, R11, R12, R25, R26, R27, R28, R4, R8 C9 L1, L2 R1, R2, R24 R14, R7 R13, R9 R15, R19 R23 R3 R16, R17, R22 R5 R6 U1 DESCRIPTION Capacitor, ceramic, 100F, 6.3V, X5R, 20% Capacitor, ceramic, 100pF, 50V, NPO, 5% Capacitor, ceramic, 6800pF, 50V, X7R, 10% Capacitor, poscap, 470F, 6.3V, electrolytic 20% Capacitor, ceramic, 0.1F, 16V, X7R, 10% Capacitor, ceramic, 1.00F, 16V, X7R, 10% Not installed Capacitor, ceramic, 0.01F, 50V, X7R, 10% Inductor, 1H, 19A, 20% Resistor, thick film, 100k, 1/10W, 1% Resistor, thick film, 1.0k, 1/10W, 1% Resistor, thick film, 887, 1/10W, 1% Resistor, alloy metal, 5m, 1W, 1% Resistor, manganin-foil, 0, 2W Resistor, thick film, 30.9k, 1/10W, 1% Resistor, thick film, 0, 1/10W Resistor, thick film, 4.75k, 1/10W, 1% Resistor, thick film, 7.15k, 1/10W, 1% BGA Power Block SIZE 1812 0603 0603 7343 0603 0805 0603 13.0mm X 12.9mm 0603 0603 0603 2512 2716 0603 0603 0603 0603 9.25mm X 15.5mm MFR TDK Phycomp KOA Sanyo Murata Murata Samsung Panasonic KOA KOA KOA Panasonic Isotek Corp KOA ROHM KOA KOA IR PART NUMBER C4532X5R0J107M 0603CG101J9B20 X7R0603HTTD682K 6TPB470M GRM188R71C104KA01D GRM40X7R105K016 CL10B103KBNC ETQP1H1R0BFA RK73H1J1003F RK73H1J1001F RK73H1J8870F ERJM1WSF5M0U SMT-R000 RK73H1J3092F MCR03EZHJ000 RK73H1JLTD4751F RK73H1JLTD7151F IP1201 Table 2. Reference Design Bill of Materials www.irf.com 27 IP1201 0.15 [.006] C 2X 6 15.50 [.610] B A 5 C 0.45 [.0177] 0.35 [.0138] 0.12 [.005] C BALL A1 CORNER ID 9.25 [.364] NOTES : DIMENS IONING & T OLERANCING PER ASME Y14.5M-1994. DIMENS IONS ARE SHOWN IN MILLIMET ERS [INCHES ]. CONT ROLLING DIMENS ION: MILLIMET ER S OLDER BALL POSIT ION DES IGNAT ION PER JESD 95-1, S PP-010. PRIMARY DAT UM C (SEAT ING PLANE) IS DEF INED BY THE S PHERICAL CROWNS OF T HE S OLDER BALLS. 6 BILATERAL TOLERANCE ZONE IS APPLIED T O EACH SIDE OF T HE PACKAGE BODY. 7 S OLDER BALL DIAMET ER IS MEAS URED AT THE MAXIMUM SOLDER BALL DIAMET ER, IN A PLANE PARALLEL T O DATUM C. 8. NOT TO S CALE. 1. 2. 3. 4. 5 0.15 [.006] C 2X 6 T OP VIEW 27X 0.80 [.032] 0.40 [.016] 2X 0.55 [.0216] 159X O 0.45 [.0178] 0.15 [.006] 0.08 [.003] (2X 0.625 [.025]) 7 2.33 [.0917] 2.11 [.0831] 2.78 [.1094] 2.46 [.0968] BOT T OM VIEW CAB C S IDE VIEW Mechanical Drawing Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR Technology products: AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifiers iPOWIR Technology BGA Packages This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGAs on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1047: Graphical solution to two branch heatsinking Safe Operating Area This paper is a suppliment to AN-1030 and explains how to use the double side Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. 28 www.irf.com IP1201 BALL A1 IDENTIFIER DATE CODE (YYWW) YY=YEAR WW=WEEK PART NUMBER FACTORY CODE INTERNATONAL RECTIFIER LOGO ASSEMBLY CODE 0250 XXXX IP1201 Part Marking 0250 XXXX IP1201 0250 XXXX IP1201 24.00 (.945) 20.00 (.787) FEED DIRECT ION NOT ES : 1. OUT LINE CONFORMS T O EIA-481 & EIA-541. IP1201, BGA Tape & Reel Information Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.10/03 www.irf.com 29 |
Price & Availability of IP1201
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |